SH7125_08 Datasheet, PDF (345/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
MPφ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
TGR
N
Figure 9.92 Counter Clear Timing (Input Capture)
Buffer Operation Timing: Figures 9.93 to 9.95 show the timing in buffer operation.
MPφ
TCNT
n
n+1
Compare
match buffer
signal
TGRA,
TGRB
n
N
TGRC,
TGRD
N
Figure 9.93 Buffer Operation Timing (Compare Match)
MPφ
Input capture
signal
TCNT
N
N+1
TGRA,
TGRB
n
N
N+1
TGRC,
TGRD
n
N
Figure 9.94 Buffer Operation Timing (Input Capture)
Rev. 4.00 Jul. 25, 2008 Page 325 of 750
REJ09B0243-0400