SH7125_08 Datasheet, PDF (763/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
17.4.2 (5) Flash Transfer
Destination Address Register
(FTDAR)
Page Revision (See Manual for Details)
591 Amended
FTDAR specifies the on-chip RAM address to which the
on-chip program is downloaded.
Make settings for FTDAR before writing 1 to the SCO bit
in FCCS. The initial value is H'00. which points to the
start address (H'FFFFA000) in on-chip RAM.
592 Amended
Initial
Bit Bit Name Value R/W Description
6 to TDA[6:0]
0
All 0 R/W •••
H'00, H'01, H'05 to H'7F:
Setting prohibited when
downloading by the SCO bit with
user program mode. If this value
is set, the TDER bit (bit 7) is set
to 1 to abort the download
processing. When not using user
program mode, set H'00 to the
TDA bits.
Table 21.1 Absolute Maximum
Ratings
707
Deleted
Item
Symbol
Analog power supply voltage AV_CC
Analog reference voltage
AV_ref
Analog input voltage
V_an
Value
Unit
-0.3 to + 7.0
V
-0.3 to AV_CC + 0.3 V
-0.3 to AV_CC + 0.3 V
Table 21.2 DC Characteristics
709
Amended
Item
Symbol Min.
Typ.
Output high TIOC3B, TIOC3D, V
OH
voltage
TIOC4A to TIOC4D
V - 0.8 —
CC
Output low TIOC3B, TIOC3D, V
OL
—
—
voltage
TIOC4A to TIOC4D
—
—
—
—
Max. Unit
—
V
1.0 V
0.6 V
0.4 V
Test
Conditions
I = –5 mA,
OH
V = 4.5 V
CC
to 5.5 V
I = 15 mA,
OL
V = 4.5 V
CC
to 5.5 V
I = 10 mA,
OL
V = 4.5 V
CC
to 5.5 V
I = 8 mA,
OL
V = 4.5 V
CC
to 5.5 V
Rev. 4.00 Jul. 25, 2008 Page 743 of 750
REJ09B0243-0400