SH7125_08 Datasheet, PDF (239/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.3.19 Timer Output Control Register 2 (TOCR2)
TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output
in complementary PWM mode and reset-synchronized PWM mode.
Bit: 7
6
5
4
3
2
1
0
BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7, 6 BF[1:0]
00
R/W TOLBR Buffer Transfer Timing Select
These bits select the timing for transferring data from
TOLBR to TOCR2.
For details, see table 9.32.
5
OLS3N
0
R/W Output Level Select 3N*
This bit selects the output level on TIOC4D in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.33.
4
OLS3P
0
R/W Output Level Select 3P*
This bit selects the output level on TIOC4B in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.34.
3
OLS2N
0
R/W Output Level Select 2N*
This bit selects the output level on TIOC4C in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.35.
2
OLS2P
0
R/W Output Level Select 2P*
This bit selects the output level on TIOC4A in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.36.
1
OLS1N
0
R/W Output Level Select 1N*
This bit selects the output level on TIOC3D in reset-
synchronized PWM mode/complementary PWM mode.
See table 9.37.
Rev. 4.00 Jul. 25, 2008 Page 219 of 750
REJ09B0243-0400