SH7125_08 Datasheet, PDF (642/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
Note that the reset signal should only be released after providing a reset input over a period longer
than the normal 100 µs. Since high voltages are applied during programming/erasing of the flash
memory, some voltage may still remain even after the error protection state has been entered. For
this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset
period so that the charge is released.
The state-transition diagram in figure 17.13 shows transitions to and from the error protection
state.
Program mode
Erase mode
RES = 0
Reset or standby
(Hardware protection)
Read disabled
Programming/erasing
enabled
FLER = 0
Error occurred
Er(rSorofotwccaurerresdtandby_{R) ES = 0}
Read enabled
Programming/erasing disabled
FLER = 0
RES = 0
Programming/erasing interface
register is in its initial state.
Error protection mode Software standby mode
Error protection mode
(Software standby)
Read enabled
Programming/erasing disabled
FLER = 1
Cancel
software standby
mode
Read disabled
Programming/erasing disabled
FLER = 1
Programming/erasing interface
register is in its initial state.
Figure 17.13 Transitions to and from Error Protection State
Rev. 4.00 Jul. 25, 2008 Page 622 of 750
REJ09B0243-0400