SH7125_08 Datasheet, PDF (315/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
15. Counter Clearing by TGRA_3 Compare Match
In complementary PWM mode, by setting the CCE bit in the timer waveform control register
(TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare
match.
Figure 9.62 illustrates an operation example.
Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest)
2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to
SYNC4 bits in the timer synchronous register (TSYR) to 1 or the CE0A, CE0B, CE0C,
CE0D, CE1A, CE1B, CE1C, and CE1D bits in the timer synchronous clear register
(TSYCR) to 1).
3. Do not set the PWM duty value to H'0000.
4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1.
TGRA_3
Counter cleared
by TGRA_3 compare match
TCDR
TGRB_3
TDDR
H'0000
Output waveform
Output waveform
Output waveform is active-high.
Figure 9.62 Example of Counter Clearing Operation by TGRA_3 Compare Match
Rev. 4.00 Jul. 25, 2008 Page 295 of 750
REJ09B0243-0400