SH7125_08 Datasheet, PDF (765/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Index
A
A/D conversion time............................... 492
A/D converter (ADC) ............................. 475
A/D converter activation......................... 319
A/D converter characteristics.................. 726
A/D converter interrupt source ............... 495
A/D converter start request delaying
function................................................... 308
Absolute accuracy................................... 496
Absolute maximum ratings..................... 707
AC characteristics................................... 711
AC characteristics measurement
conditions ............................................... 725
Address error .............................. 77, 86, 660
Addressing modes..................................... 26
Arithmetic operation instructions ............. 39
Asynchronous mode ....................... 411, 444
Clock synchronous mode ................ 411, 454
Clock timing ........................................... 712
CMT interrupt sources ............................ 509
Compare match timer (CMT) ................. 503
Complementary PWM mode .................. 267
Connecting crystal resonator..................... 66
Continuous scan mode ............................ 489
Control signal timing .............................. 714
CPU........................................................... 17
Crystal oscillator ....................................... 57
D
Data transfer instructions .......................... 37
DC Characteristics .................................. 708
Dead time compensation......................... 313
Divider ...................................................... 57
B
Boot mode .............................................. 607
Branch instructions ................................... 43
Break comparison conditions ................. 113
Break detection and processing .............. 472
Break on data access cycle ..................... 135
Break on instruction fetch cycle ............. 135
Bus state controller (BSC) ...................... 147
C
Calculating exception handling
vector table addresses ............................... 74
Changing frequency.................................. 65
Clock (MPφ) for the MTU2 module ......... 55
Clock frequency control circuit ................ 57
Clock operating mode............................... 59
Clock pulse generator (CPG).................... 55
E
Error protection....................................... 621
Exception handling ................................... 71
Exception handling state ........................... 47
External clock input method ..................... 67
External pulse width measurement ......... 312
External trigger input timing................... 493
F
Features of instructions ............................. 23
Flash Memory ......................................... 575
Flash memory characteristics.................. 727
Flash memory configuration ................... 580
Flow of the user break operation............. 134
Full-scale error ........................................ 496
Function for detecting oscillator stop........ 68
Rev. 4.00 Jul. 25, 2008 Page 745 of 750
REJ09B0243-0400