SH7125_08 Datasheet, PDF (357/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.8 Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 9.112 shows the timing in this case.
MPφ
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 9.112 Contention between Buffer Register Write and TCNT Clear
Rev. 4.00 Jul. 25, 2008 Page 337 of 750
REJ09B0243-0400