SH7125_08 Datasheet, PDF (531/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Compare Match Timer (CMT)
14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the
timing to write to CMCNT in words.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
CMCNT count-up
enable
CMCNT
N
M (CMCNT write data)
Figure 14.6 Conflict between Word-Write and Count-Up Processes of CMCNT
Rev. 4.00 Jul. 25, 2008 Page 511 of 750
REJ09B0243-0400