SH7125_08 Datasheet, PDF (46/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
Table 2.7 Access with Displacement
Type
CPU in this LSI
16-bit displacement MOV.W @(disp,PC),R0
MOV.W @(R0,R1),R2
........
.DATA.W H'1234
Note: * Immediate data is referenced by @(disp,PC).
Example of Other CPUs
MOV.W @(H'1234,R1),R2
2.4.2 Addressing Modes
Table 2.8 lists addressing modes and effective address calculation methods.
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format Effective Address Calculation Method
Register
Rn
direct
Effective address is register Rn.
(Operand is register Rn contents.)
Register
indirect
@Rn
Effective address is register Rn contents.
Rn
Rn
Register
@Rn+
indirect with
post-increment
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4
+
Register
@–Rn
indirect with
pre-decrement
1/2/4
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn
Rn - 1/2/4
-
Rn - 1/2/4
1/2/4
Calculation
Formula

Rn
Rn
After instruction
execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4
→ Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4
→ Rn
(Instruction
executed with Rn
after calculation)
Rev. 4.00 Jul. 25, 2008 Page 26 of 750
REJ09B0243-0400