SH7125_08 Datasheet, PDF (83/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Bit
8 to 6
5 to 3
2 to 0
Initial
Bit Name Value
PFC[2:0] 011

011
MPFC[2:0] 011
R/W Description
R/W Peripheral Clock (Pφ) Frequency Division Ratio
Specify the division ratio of the peripheral clock (Pφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
R/W Reserved
These bits are always read as B'011. The write value
should always be B'011.
R/W MTU2 Clock (MPφ) Frequency Division Ratio
Specify the division ratio of the MTU2 clock (MPφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: Setting prohibited
001: ×1/2
010: Setting prohibited
011: ×1/4 (initial value)
100: ×1/8
Other than above: Setting prohibited
Rev. 4.00 Jul. 25, 2008 Page 63 of 750
REJ09B0243-0400