SH7125_08 Datasheet, PDF (145/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
7.2.10 Break Bus Cycle Register B (BBRB)
BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel B.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
CPB[2:0]
CDB[1:0]
IDB[1:0]
RWB[1:0]
SZB[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 8 CPB[2:0] 000
R/W Bus Master Select B for I Bus
Select the bus master when the I bus is selected as
the bus cycle of the channel B break condition.
However, when the L bus is selected as the bus cycle,
the setting of the CPB2 to CPB0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: Setting prohibited
1xx: Setting prohibited
7, 6
CDB[1:0] 00
R/W L Bus Cycle/I Bus Cycle Select B
Select the L bus cycle or I bus cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Rev. 4.00 Jul. 25, 2008 Page 125 of 750
REJ09B0243-0400