SH7125_08 Datasheet, PDF (170/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Bus State Controller (BSC)
period is required because Iclk ≥ Bclk ≥ Pclk. In the case shown in figure 8.3, where n = 0 and m
= 1, the period required for access by the CPU is 3 × Iclk + 2 × Bclk + 2 × Pclk + 2 × Iclk.
Iclk
L bus
Bclk
I bus
Pclk
Peripheral bus
Figure 8.3 Timing of Read Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:2:1)
Rev. 4.00 Jul. 25, 2008 Page 150 of 750
REJ09B0243-0400