SH7125_08 Datasheet, PDF (165/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 7 User Break Controller (UBC)
8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a
SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a
SLEEP instruction or one or two instructions before a SLEEP instruction.
Rev. 4.00 Jul. 25, 2008 Page 145 of 750
REJ09B0243-0400