SH7125_08 Datasheet, PDF (695/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 20 List of Registers
Section 20 List of Registers
This section gives information on internal I/O registers. The contents of this section are as follows:
1. Register Address Table (in the order from a lower address)
• Registers are listed in the order from lower allocated addresses.
• As for reserved addresses, the register name column is indicated with . Do not access
reserved addresses.
• As for 16- or 32-bit address, the MSB addresses are shown.
• The list is classified according to module names.
• The numbers of access cycles are given.
2. Register Bit Table
• Bit configurations are shown in the order of the register address table.
• As for reserved bits, the bit name column is indicated with .
• As for the blank column of the bit names, the whole register is allocated to the counter or data.
• As for 16- or 32-bit registers, bits are indicated from the MSB.
3. Register State in Each Operating Mode
• Register states are listed in the order of the register address table.
• Register states in the basic operating mode are shown. As for modules including their specific
states such as reset, see the sections of those modules.
Rev. 4.00 Jul. 25, 2008 Page 675 of 750
REJ09B0243-0400