SH7125_08 Datasheet, PDF (22/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
Table 1.1 Features
Items
CPU
Operating modes
User break controller
(UBC)
On-chip ROM
On-chip RAM
Specification
• Central processing unit with an internal 32-bit RISC (Reduced
Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between
registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)
executed in two to five cycles
• C language-oriented 62 basic instructions
Note:
Some specifications on slot illegal instruction exception handling
in this LSI differ from those of the conventional SH-2. For details,
see section 5.8.4, Notes on Slot Illegal Instruction Exception
Handling.
• Operating modes
 Single chip mode
• Operating states
 Program execution state
 Exception handling state
• Power-down modes
 Sleep mode
 Software standby mode
 Module standby mode
• Addresses, data values, type of access, and data size can all be set as
break conditions
• Supports a sequential break function
• Two break channels
• 128 kbytes (SH71253, SH71243)
• 64 kbytes (SH71252, SH71242)
• 32 kbytes (SH71241)
• 8 kbytes
Rev. 4.00 Jul. 25, 2008 Page 2 of 750
REJ09B0243-0400