SH7125_08 Datasheet, PDF (532/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Compare Match Timer (CMT)
14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing
has priority over the count-up. In this case, the count-up is not performed. The byte data on
another side, which is not written to, is also not counted and the previous contents remain.
Figure 14.7 shows the timing when the count-up occurs in the T2 cycle while writing to CMCNT
in bytes.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNTH
Internal write
CMCNT count-up
enable
CMCNTH
N
M (CMCNT write data)
CMCNTL
X
X
Figure 14.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
14.5.5 Compare Match between CMCNT and CMCOR
Do not set the same value in CMCNT and CMCOR while CMCNT is not counting. If set, the
CMF bit in CMCSR is set to 1 and CMCNT is cleared to H'0000.
Rev. 4.00 Jul. 25, 2008 Page 512 of 750
REJ09B0243-0400