SH7125_08 Datasheet, PDF (417/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
Pφ
POE input
Pφ rising edge
Falling edge detection
PE9/TIOC3B
High-impedance state*
Note: * The other high-current pins also enter the high-impedance state in the similar timing.
Figure 10.2 Falling Edge Detection
(2) Low-Level Detection
Figure 10.3 shows the low-level detection operation. Sixteen continuous low levels are sampled
with the sampling clock selected by ICSR1. If even one high level is detected during this interval,
the low level is not accepted.
The timing when the high-current pins enter the high-impedance state after the sampling clock is
input is the same in both falling-edge detection and in low-level detection.
8/16/128 clock
cycles
Pφ
Sampling
clock
POE input
PE9/
TIOC3B
High-impedance
state*
When low level is
Flag set
sampled at all points ¹
2
3
16 _{(POE received)}
When high level is
sampled at least once
1
2
13 Flag not set
Note: * Other high-current pins also go to the high-impedance state at the same timing.
Figure 10.3 Low-Level Detection Operation
Rev. 4.00 Jul. 25, 2008 Page 397 of 750
REJ09B0243-0400