SH7125_08 Datasheet, PDF (301/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3 and TCNT_4 values
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
TGRA_4
Initial output
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT_3 and TCNT_4 count start
(TSTR setting)
Figure 9.45 Example of Initial Output in Complementary PWM Mode (2)
Rev. 4.00 Jul. 25, 2008 Page 281 of 750
REJ09B0243-0400