SH7125_08 Datasheet, PDF (410/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
Bit
Bit Name
15 to 13 —
12
POE8F
11, 10 
9
POE8E
8
PIE3
Initial
value
All 0
0
All 0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*¹ POE8 Flag
This flag indicates that a high impedance request has
been input to the POE8 pin.
[Clearing conditions]
• By writing 0 to POE8F after reading POE8F = 1
(when the falling edge is selected by bits 1 and 0 in
ICSR3)·
• By writing 0 to POE8F after reading POE8F = 1 after
a high level input to POE8 is sampled at Pf/8, Pf/16,
or Pf/128 clock (when low-level sampling is selected
by bits 1 and 0 in ICSR3)
[Setting condition]
• When the input condition set by bits 1 and 0 in
ICSR3 occurs at the POE8 pin
R
Reserved
R/W*²
These bits are always read as 0. The write value should
always be 0.
POE8 High-Impedance Enable
This bit specifies whether to place the pins in high-
impedance state when the POE8F bit in ICSR3 is set
to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
R/W Port Interrupt Enable 3
(Supported only by the SH7125. Write 0 to this bit in the
SH7124.)
This bit enables or disables interrupt requests when the
POE8 bit in ICSR3 is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
Rev. 4.00 Jul. 25, 2008 Page 390 of 750
REJ09B0243-0400