SH7125_08 Datasheet, PDF (405/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
10.3.1 Input Level Control/Status Register 1 (ICSR1)
ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1, and POE3 pin input
modes, controls the enable/disable of interrupts, and indicates status.
Bit: 15 14 13 12 11 10
POE3F - POE1F POE0F -
-
Initial value: 0
0
0
0
0
0
R/W:R/(W)*¹R/(W)*¹R/(W)*¹ R/(W)*¹ R
R
9
8
7
6
5
4
3
2
1
0
-
PIE1 POE3M[1:0]
-
-
POE1M[1:0] POE0M[1:0]
0
0
0
0
0
0
0
0
0
0
R R/W R/W*² R/W*² R/W*² R/W*² R/W*² R/W*² R/W*² R/W*²
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. Can be modified only once after a power-on reset.
Initial
Bit Bit Name value R/W Description
15
POE3F
0
R/(W)*¹ POE3 Flag
(Supported only by the SH7125.)
This flag indicates that a high impedance request has
been input to the POE3 pin.
[Clearing conditions]
• By writing 0 to POE3F after reading POE3F = 1
(when the falling edge is selected by bits 7 and 6 in
ICSR1)
• By writing 0 to POE3F after reading POE3F = 1 after
a high level input to POE3 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 7 and 6 in ICSR1)
[Setting condition]
• When the input set by ICSR1 bits 7 and 6 occurs at
the POE3 pin
14

0
R/(W)*¹ Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Jul. 25, 2008 Page 385 of 750
REJ09B0243-0400