SH7125_08 Datasheet, PDF (679/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 18 RAM
Section 18 RAM
This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a
32-bit data bus (L bus), enabling 8, 16, or 32-bit width access to data in the on-chip RAM.
The on-chip RAM is allocated to different addresses according to each product as shown in figure
18.1. The on-chip RAM can be accessed from the CPU (via the L bus). An access from the L bus
(CPU) is a 1-cycle access. In addition, the contents of the on-chip RAM are retained in sleep mode
or software standby mode, and at a power-on reset or manual reset.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the RAM control
register (RAMCR). For details on the RAM control register (RAMCR), refer to section 19.3.7,
RAM Control Register (RAMCR).
H'FFFFA000
H'FFFFBFFF
Page 1
8 kbytes
SH7125/SH7124
(8 kbytes)
Figure 18.1 On-chip RAM Addresses
RAM0200A_010020030800
Rev. 4.00 Jul. 25, 2008 Page 659 of 750
REJ09B0243-0400