SH7125_08 Datasheet, PDF (507/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 13 A/D Converter (ADC)
Bit
7 to 4
Bit Name
TRG1S[3:0]
Initial
Value
0000
R/W Description
R/W A/D Trigger 1 Select 3 to 0
Select an external trigger or MTU2 trigger to start A/D
conversion for group 0 when A/D module 1 is in single
mode, 4-channel scan mode, or 2-channel scan mode.
0000: External trigger pin (ADTRG) input
0001: TRGA input capture/compare match for each
MTU2 channel or TCNT_4 underflow (trough) in
complementary PWM mode (TRGAN)
0010: MTU2 channel 0 compare match (TRG0N)
0011: MTU2 A/D conversion start request delaying
(TRG4AN)
0100: MTU2 A/D conversion start request delaying
(TRG4BN)
0101: Setting prohibited
0110: Setting prohibited
0111: Setting prohibited
1xxx: Setting prohibited
When switching the selector, first clear the ADST bit in
the A/D control register (ADCR) to 0.
Specify different trigger sources for the group 0 and
group 1 conversion requests so that a group 0
conversion request is not generated simultaneously
with a group 1 conversion request in 2-channel scan
mode.
Rev. 4.00 Jul. 25, 2008 Page 487 of 750
REJ09B0243-0400