SH7125_08 Datasheet, PDF (359/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
9.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel
5, write to TGR is performed and the input capture signal is generated.
Figures 9.115 and 9.116 show the timing in this case.
MPφ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T1 T2
TGR address
M
TGR
M
Figure 9.115 Contention between TGR Write and Input Capture (Channels 0 to 4)
MPφ
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1 T2
TGR address
M
TGR write data
N
Figure 9.116 Contention between TGR Write and Input Capture (Channel 5)
Rev. 4.00 Jul. 25, 2008 Page 339 of 750
REJ09B0243-0400