SH7125_08 Datasheet, PDF (419/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
10.5 Interrupts
The POE issues a request to generate an interrupt when the specified condition is satisfied during
input level detection or output level comparison. Table 10.5 shows the interrupt sources and their
conditions.
Table 10.5 Interrupt Sources and Conditions
Name
OEI1
OEI3
Interrupt Source
Output enable interrupt 1
Output enable interrupt 2
Interrupt Flag
POE3F, POE1F, POE0F,
and OSF1
POE8F
Condition
PIE1 • (POE3F + POE1F +
POE0F) + OIE1 • OSF1
PIE3 • POE8F
Rev. 4.00 Jul. 25, 2008 Page 399 of 750
REJ09B0243-0400