SH7125_08 Datasheet, PDF (220/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
1
CMFV5
0
R/(W)*¹ Compare Match/Input Capture Flag V5
Status flag that indicates the occurrence of TGRV_5 input
capture or compare match.
[Setting conditions]
• When TCNTV_5 = TGRV_5 and TGRV_5 is
functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by
input capture signal and TGRV_5 is functioning as
input capture register
• When TCNTV_5 value is transferred to TGRV_5 and
TGRV_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
register V_5 (TIORV_5)*²
[Clearing condition]
• When 0 is written to CMFV5 after reading CMFV5 = 1
Rev. 4.00 Jul. 25, 2008 Page 200 of 750
REJ09B0243-0400