SH7125_08 Datasheet, PDF (594/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 I/O Ports
16.4.2 Port F Data Register L (PFDRL)
The port F data register L (PFDRL) is a 16-bit read-only register that stores port F data. Bits
PF7DR to PF0DR correspond to pins PF7 to PF0 (multiplexed functions omitted here) in the
SH7125 and SH7124.
Any value written into these bits is ignored, and there is no effect on the state of the pins. When
any of the bits are read, the pin state rather than the bit value is read directly. However, when an
A/D converter analog input is being sampled, values of 1 are read. Table 16.8 summarizes port F
data register L read/write operations.
• PFDRL (SH7125, SH7124)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
DR DR DR DR DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
15 to 8 
All 0
R
7
PF7DR Pin state R
6
PF6DR Pin state R
5
PF5DR Pin state R
4
PF4DR Pin state R
3
PF3DR Pin state R
2
PF2DR Pin state R
1
PF1DR Pin state R
0
PF0DR Pin state R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
See table 16.8.
Table 16.8 Port F Data Register L (PFDRL) Read/Write Operations
• PFDRL Bits 7 to 0
Pin Function
General input
ANn input
Read
Pin state
1
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Rev. 4.00 Jul. 25, 2008 Page 574 of 750
REJ09B0243-0400