SH7125_08 Datasheet, PDF (590/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 16 I/O Ports
• PEDRL (SH7124)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8
DR DR DR DR DR DR DR DR
-
-
-
-
PE3 PE2 PE1 PE0
DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W R/W R/W
Bit
15
14
13
12
11
10
9
8
7 to 4
3
2
1
0
Initial
Bit Name Value
PE15DR 0
PE14DR 0
PE13DR 0
PE12DR 0
PE11DR 0
PE10DR 0
PE9DR 0
PE8DR 0

All 0
PE3DR 0
PE2DR 0
PE1DR 0
PE0DR 0
R/W Description
R/W See table 16.6.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W See table 16.6.
R/W
R/W
R/W
Table 16.6 Port E Data Register L (PEDRL) Read/Write Operations
• PEDRL Bits 15 to 0
PEIOR Pin Function
0
General input
Other than
general input
1
General output
Other than
general output
Read
Pin state
Pin state
PEDRL value
PEDRL value
Write
Can write to PEDRL, but it has no effect on pin
state
Can write to PEDRL, but it has no effect on pin
state
Value written is output from pin
Can write to PEDRL, but it has no effect on pin
state
Rev. 4.00 Jul. 25, 2008 Page 570 of 750
REJ09B0243-0400