SH7125_08 Datasheet, PDF (80/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Table 4.4 Frequency Division Ratios Specifiable with FRQCR
PLL
Multipli-
FRQCR Division Ratio
Setting
cation
Ratio
Iφ Bφ Pφ MPφ Iφ
Clock Ratio
Bφ Pφ MPφ
Clock Frequency (MHz)*
Input
Clock Iφ
Bφ Pφ MPφ
×8
1/8 1/8 1/8 1/8 1
1
1
1
10
10 10 10 10
1/4 1/8 1/8 1/8 2
1
1
1
10
20 10 10 10
1/4 1/4 1/4 1/4 2
2
2
2
10
20 20 20 20
1/2 1/4 1/4 1/4 4
2
2
2
10
40 20 20 20
1/2 1/2 1/2 1/2 4
4
4
4
10
40 40 40 40
1/8 1/8 1/8 1/8 1
1
1
1
12.5
12.5 12.5 12.5 12.5
1/4 1/8 1/8 1/8 2
1
1
1
12.5
25 12.5 12.5 12.5
1/4 1/4 1/4 1/4 2
2
2
2
12.5
25 25 25 25
1/2 1/4 1/4 1/4 4
2
2
2
12.5
50 25 25 25
Notes: *
Clock frequencies when the input clock frequency is assumed to be the shown value.
The internal clock (Iφ) frequency must be 10 to 50 MHz and the peripheral clock (Pφ)
frequency must be 10 to 40 MHz. The bus clock (Bφ) frequency must be equal to the
peripheral clock (Pφ) frequency.
1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1/2,
×1/4, and ×1/8 for each clock by the setting in the frequency control register.
2. The output frequency of the PLL circuit is the product of the frequency of the input from
the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit.
3. The input to the divider is always the output from the PLL circuit.
4. The internal clock (Iφ) frequency is the product of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 50 MHz
(maximum operating frequency).
5. The peripheral clock (Pφ) frequency is the product of the frequency of the input from the
crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the
division ratio of the divider. The resultant frequency must be a maximum of 40 MHz.
6. When using the MTU2, the MTU2 clock (MPφ) frequency must be equal to or higher
than the peripheral clock frequency (Pφ). The MTU2 clock (MPφ) frequency are the
product of the frequency of the input from the crystal resonator or EXTAL pin, the
multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider.
7. The frequency of the CK pin is always be equal to the bus clock (Bφ) frequency.
8. The bus clock (Bφ) frequency must be equal to the peripheral clock (Pφ) frequency.
Rev. 4.00 Jul. 25, 2008 Page 60 of 750
REJ09B0243-0400