SH7125_08 Datasheet, PDF (101/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

5.5 Exceptions Triggered by Instructions
Section 5 Exception Handling
5.5.1 Types of Exceptions Triggered by Instructions
Exception handling can be triggered by the trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Table 5.9 Types of Exceptions Triggered by Instructions
Type
Source Instruction
Comment
Trap instruction TRAPA

Illegal slot
instructions*
Undefined code placed
immediately after a delayed
branch instruction (delay slot) or
instructions that changes the PC
value
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that changes the PC value: JMP,
JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, LDC Rm,SR,
LDC.L @Rm+,SR
General illegal Undefined code anywhere

instructions*
besides in a delay slot
Note: * The operation is not guaranteed when undefined instructions other than H'F000 to
H'FFFF are decoded.
5.5.2 Trap Instructions
When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The CPU reads the start address of the exception handling routine from the exception handling
vector table that corresponds to the vector number specified in the TRAPA instruction,
program execution branches to that address, and then the program starts. This branch is not a
delayed branch.
Rev. 4.00 Jul. 25, 2008 Page 81 of 750
REJ09B0243-0400