SH7125_08 Datasheet, PDF (129/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Interrupt Controller (INTC)
Program
execution state
Interrupt?
No
Yes
No
User break?
Yes
No
NMI?
Yes
I3 to I0 ≤
Yes
level 14?
No
Yes
IRQOUT = low ^*1*3
Level 15
No
interrupt?
Yes
I3 to I0 ≤
level 14?
No
Yes
Level 14
interrupt?
Yes
I3 to I0 ≤
level 13?
No
Level 1
No
interrupt?
Yes
No
Yes
I3 to I0 =
level 0?
No
Save SR to stack
Save PC to stack
Copy interrupt
level to I3 to I0
IRQOUT = high ^*2*3
Read exception
vector table
Branch to exception
handling routine
Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU
1. IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1).
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
3. The IRQOUT pin change timing depends on a frequency dividing ratio between the internal (Iφ) and bus (Bφ)
clocks. This flowchart shows that the frequency dividing ratios of the internal (Iφ) and bus (Bφ) clocks are the same.
Figure 6.3 Interrupt Sequence Flowchart
Rev. 4.00 Jul. 25, 2008 Page 109 of 750
REJ09B0243-0400