SH7125_08 Datasheet, PDF (675/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
table, interrupt processing routine, and user branch program should be transferred to on-chip
RAM before programming/erasing of the flash memory starts.
5. The flash memory is not accessible during programming/erasing operations. Therefore, the
programming/erasing program must be downloaded to on-chip RAM in advance. Areas for
executing each procedure program for initiating programming/erasing, the user program at the
user branch destination for programming/erasing, the interrupt vector table, and the interrupt
processing routine must be located in on-chip RAM.
6. After programming/erasing, access to flash memory is inhibited until FKEY is cleared.
A reset state (RES = 0) for more than at least 100 µs must be taken when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Transitions to the reset state during programming/erasing are inhibited. When the reset signal
is accidentally input to the LSI, a longer period in the reset state than usual (100 µs) is needed
before the reset signal is released.
7. When the program data storage area indicated by the FMPDR parameter in the programming
processing is within the flash memory area, an error will occur. Therefore, temporarily transfer
the program data to on-chip RAM to change the address set in FMPDR to an address other
than flash memory.
Tables 17.16 and 17.17 show the areas in which the program data can be stored and executed
according to the operation type and mode.
Table 17.16 Executable MAT
Operation
Programming
Erasing
Initiated Mode
User Program Mode
Table 17.17 (1)
Table 17.17 (2)
Rev. 4.00 Jul. 25, 2008 Page 655 of 750
REJ09B0243-0400