SH7125_08 Datasheet, PDF (97/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

5.3 Address Errors
Section 5 Exception Handling
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data is read from or written to, as shown in
table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Master
Instruction CPU
fetch
Data
CPU
read/write
Bus Cycle Description
Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from a space other than
on-chip peripheral module space
Instruction fetched from on-chip peripheral
module space
Word data accessed from even address
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Byte or word data accessed in on-chip
peripheral module space
Longword data accessed in 16-bit on-chip
peripheral module space
Longword data accessed in 8-bit on-chip
peripheral module space
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
None (normal)
None (normal)
Rev. 4.00 Jul. 25, 2008 Page 77 of 750
REJ09B0243-0400