SH7125_08 Datasheet, PDF (190/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIORL_0, TIORL_3, TIORL_4
Bit: 7
6
5
4
3
2
1
0
IOD[3:0]
IOC[3:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3
Specify the function of TGRD.
See the following tables.
TIORL_0: Table 9.13
TIORL_3: Table 9.17
TIORL_4: Table 9.19
3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3
Specify the function of TGRC.
See the following tables.
TIORL_0: Table 9.21
TIORL_3: Table 9.25
TIORL_4: Table 9.27
• TIORU_5, TIORV_5, TIORW_5
Bit name: 7
6
-
-
Initial value: 0
0
R/W: R
R
5
4
3
2
1
0
-
IOC[4:0]
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Bit
Bit Name
7 to 5 
4 to 0 IOC[4:0]
Initial
Value
All 0
00000
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
I/O Control C0 to C4
Specify the function of TGRU_5, TGRV_5, and
TGRW_5.
For details, see table 9.28.
Rev. 4.00 Jul. 25, 2008 Page 170 of 750
REJ09B0243-0400