SH7125_08 Datasheet, PDF (734/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 21 Electrical Characteristics
21.3.2 Control Signal Timing
Table 21.6 Control Signal Timing
Conditions: V_CC = AV_CC = 4.0 V to 5.5 V, V_SS = PLLV_SS = AV_SS = 0 V,
T_a = –20 to +85°C (consumer specifications),
T_a = –40 to +85°C (industrial specifications)
Item
Symbol Min.
Max.
Unit Reference Figure
RES pulse width
t_RESW
20*²
—
RES setup time*¹ (reference values)
t_RESS
65
—
RES hold time (reference values)
t_RESH
15
—
MRES pulse width
t_MRESW
20*³
—
MRES setup time*¹ (reference values) t_MRESS
25
—
MRES hold time (reference values)
t_MRESH
15
—
MD1, FWE setup time
t_MDS
20
—
NMI setup time*¹ (reference values)
t_NMIS
60
—
NMI hold time (reference values)
t_NMIH
10
—
IRQ3 to IRQ0 setup time*¹
(reference values)
t_IRQS
35
—
t *4
Bcyc
ns
ns
t *⁴
Bcyc
ns
ns
t *⁴
Bcyc
ns
ns
ns
Figures 21.2, 21.3,
21.5, 21.6
Figure 21.5
Figure 21.6
IRQ3 to IRQ0 hold time
(reference values)
t_IRQH
35
—
ns
IRQOUT output delay time
(reference values)
t_IRQOD
—
100
ns
Figure 21.7
Notes: 1. The RES, MRES, NMI, and IRQ3 to IRQ0 signals are asynchronous signals. When the
setup time is satisfied, change of signal level is detected at the rising edge of the clock.
If not, the detection is delayed until the rising edge of the clock.
2. In standby mode, t = t (10 ms).
RESW
OSC2
3. In standby mode, t_MRESW = t_OSC2 (10 ms).
4. t_Bcyc indicates the bus clock cycle time (Bφ = CK).
Rev. 4.00 Jul. 25, 2008 Page 714 of 750
REJ09B0243-0400