SH7125_08 Datasheet, PDF (634/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 17 Flash Memory
128-byte programming is performed in one program processing. When more than 128-byte
programming is performed, programming destination address/program data parameter is
updated in 128-byte units and programming is repeated.
When less than 128-byte programming is performed, data must total 128 bytes by adding the
invalid data. If the invalid data to be added is H'FF, the program processing period can be
shortened.
(2.1) Select the on-chip program to be downloaded
When the PPVS bit of FPCS is set to 1, the programming program is selected.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
(2.2) Write H'A5 in FKEY
If H'A5 is not written to FKEY for protection, 1 cannot be written to the SCO bit for a
download request.
(2.3) VBR is set to 0 and 1 is written to the SCO bit of FCCS, and then download is executed.
VBR must always be set to H'84000000 before setting the SCO bit to 1.
To write 1 to the SCO bit, the following conditions must be satisfied.
• H'A5 is written to FKEY.
• The SCO bit writing is executed in the on-chip RAM.
When the SCO bit is set to 1, download is started automatically. When execution returns to the
user procedure program, the SCO bit is cleared to 0. Therefore, the SCO bit cannot be
confirmed to be 1 in the user procedure program.
The download result can be confirmed only by the return value of the DPFR parameter. Before
the SCO bit is set to 1, incorrect decision must be prevented by setting the DPFR parameter,
that is one byte of the start address of the on-chip RAM area specified by FTDAR, to a value
other than the return value (H'FF).
When download is executed, particular interrupt processing, which is accompanied by the bank
switch as described below, is performed as an internal microcomputer processing, so VBR
need to be set to H'84000000. Four NOP instructions are executed immediately after the
instructions that set the SCO bit to 1.
• The user MAT space is switched to the on-chip program storage area.
• After the selection condition of the download program and the address set in FTDAR
are checked, the transfer processing is executed starting to the on-chip RAM address
specified by FTDAR.
• The SCO bits in FCCS, FPCS, and FECS are cleared to 0.
• The return value is set to the DPFR parameter.
Rev. 4.00 Jul. 25, 2008 Page 614 of 750
REJ09B0243-0400