SH7125_08 Datasheet, PDF (525/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 14 Compare Match Timer (CMT)
14.2.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is
stopped.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
- STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit
Bit Name
15 to 2 
1
STR1
0
STR0
Initial
value
All 0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Count Start 1
Specifies whether compare match counter 1 operates
or is stopped.
0: CMCNT_1 count is stopped
1: CMCNT_1 count is started
R/W Count Start 0
Specifies whether compare match counter 0 operates
or is stopped.
0: CMCNT_0 count is stopped
1: CMCNT_0 count is started
14.2.2 Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates compare match generation, enables interrupts and selects
the counter input clock.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
CMF CMIE
-
-
-
-
CKS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R (R/W)*¹ R/W R
R
R
R R/W R/W
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 4.00 Jul. 25, 2008 Page 505 of 750
REJ09B0243-0400