SH7125_08 Datasheet, PDF (407/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 10 Port Output Enable (POE)
Initial
Bit Bit Name value R/W Description
8
PIE1
0
R/W Port Interrupt Enable 1
This bit enables/disables interrupt requests when any one
of the POE0F to POE3F bits of the ICSR1 is set to 1.
0: Interrupt requests disabled
7, 6 POE3M[1:0] 00
1: Interrupt requests enabled
R/W*² POE3 mode 1, 0
(Supported only by the SH7125. Write 00 to these bits in
the SH7124.)
These bits select the input mode of the POE3 pin.
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE3 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
5, 4 
11: Accept request when POE3 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
All 0 R/W*² Reserved
3, 2 POE1M[1:0] 00
R/W*²
These bits are always read as 0. The write value should
always be 0.
POE1 mode 1, 0
These bits select the input mode of the POE1 pin.
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses and all are low level.
Rev. 4.00 Jul. 25, 2008 Page 387 of 750
REJ09B0243-0400