SH7125_08 Datasheet, PDF (487/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Initialization
[1]
Start reception
Set MPIE bit in SCSCR to 1
[2]
Read ORER and FER flags
in SCSSR
Yes
FER = 1? or ORER = 1?
No
Read RDRF flag in SCSSR
[3]
No
RDRF = 1?
Yes
Read receive data in SCRDR
No
This station’s ID?
Yes
Read ORER and FER flags
in SCSSR
[1] SCI initialization:
Set the RXD pin using the PFC.
[2] ID reception cycle:
Set the MPIE bit in SCSCR to 1.
[3] SCI status check, ID reception and
comparison:
Read SCSSR and check that the RDRF flag is
set to 1, then read the receive data in SCRDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again, and clear the RDRF flag to 0.
If the data is this station’s ID, clear the RDRF
flag to 0.
[4] SCI status check and data reception:
Read SCSSR and check that the RDRF flag is
set to 1, then read the data in SCRDR.
[5] Receive error processing and break detection:
If a receive error occurs, read the ORER and
FER flags in SCSSR to identify the error.
After performing the appropriate error
processing, ensure that the ORER and FER
flags are all cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RXD pin value.
Yes
FER = 1? or ORER = 1?
No
Read RDRF flag in SCSSR
[4]
No
RDRF = 1?
Yes
Read receive data in SCRDR
No
All data received?
[5]
Yes
Clear RE bit in SCSCR to 0
Error processing
(Continued on
next page)
<End>
Figure 12.18 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 4.00 Jul. 25, 2008 Page 467 of 750
REJ09B0243-0400