SH7125_08 Datasheet, PDF (15/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

10.4 Operation ........................................................................................................................... 396
10.4.1 Input Level Detection Operation .......................................................................... 396
10.4.2 Output-Level Compare Operation ........................................................................ 398
10.4.3 Release from High-Impedance State .................................................................... 398
10.5 Interrupts............................................................................................................................ 399
10.6 Usage Note......................................................................................................................... 400
10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer ............... 400
Section 11 Watchdog Timer (WDT) .................................................................401
11.1 Features.............................................................................................................................. 401
11.2 Input/Output Pin for WDT................................................................................................. 403
11.3 Register Descriptions ......................................................................................................... 404
11.3.1 Watchdog Timer Counter (WTCNT).................................................................... 404
11.3.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 405
11.3.3 Notes on Register Access ..................................................................................... 407
11.4 Operation ........................................................................................................................... 408
11.4.1 Canceling Software Standbys ............................................................................... 408
11.4.2 Using Watchdog Timer Mode .............................................................................. 408
11.4.3 Using Interval Timer Mode .................................................................................. 409
11.5 Usage Note......................................................................................................................... 410
Section 12 Serial Communication Interface (SCI) ............................................411
12.1 Features.............................................................................................................................. 411
12.2 Input/Output Pins............................................................................................................... 413
12.3 Register Descriptions ......................................................................................................... 414
12.3.1 Receive Shift Register (SCRSR) .......................................................................... 415
12.3.2 Receive Data Register (SCRDR) .......................................................................... 415
12.3.3 Transmit Shift Register (SCTSR) ......................................................................... 415
12.3.4 Transmit Data Register (SCTDR)......................................................................... 416
12.3.5 Serial Mode Register (SCSMR)............................................................................ 416
12.3.6 Serial Control Register (SCSCR).......................................................................... 419
12.3.7 Serial Status Register (SCSSR) ............................................................................ 422
12.3.8 Serial Port Register (SCSPTR) ............................................................................. 428
12.3.9 Serial Direction Control Register (SCSDCR)....................................................... 430
12.3.10 Bit Rate Register (SCBRR) .................................................................................. 431
12.4 Operation ........................................................................................................................... 442
12.4.1 Overview .............................................................................................................. 442
12.4.2 Operation in Asynchronous Mode ........................................................................ 444
12.4.3 Clock Synchronous Mode (Channel 1 in the SH7124 is not Available)............... 454
12.4.4 Multiprocessor Communication Function ............................................................ 463
Rev. 4.00 Jul. 25, 2008 Page xv of xx