SH7125_08 Datasheet, PDF (309/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode
Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter
clearing occurs in the Tb interval at the trough in complementary PWM mode and controls
abrupt change in duty cycle at synchronous counter clearing.
Initial output suppression is applicable only when synchronous clearing occurs in the Tb
interval at the trough as indicated by (10) or (11) in figure 9.56. When synchronous clearing
occurs outside that interval, the initial value specified by the OLS bits in TOCR is output.
Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output
period (indicated by (1) in figure 9.56) immediately after the counters start operation, initial
value output is not suppressed.
In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause
counter clearing.
Counter start
Tb interval
TGRA_3
TCDR
Tb interval
Tb interval
TCNT_3
TGRB_3
TCNT_4
TDDR
H'0000
Positive phase
Negative phase
Output waveform is active-low
(1)
(2)
(3) (4) (5) (6) (7) (8)
(9)
(10) (11)
Figure 9.56 Timing for Synchronous Counter Clearing
Rev. 4.00 Jul. 25, 2008 Page 289 of 750
REJ09B0243-0400