SH7125_08 Datasheet, PDF (542/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 15 Pin Function Controller (PFC)
15.1.1 Port A I/O Register L (PAIORL)
PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or
outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins
are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are
functioning as general-purpose inputs/outputs (PA15 to PA0). In other states, PAIORL is disabled.
A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an
input pin if the bit is cleared to 0.
However, bits 15 to 10, 5, and 2 of PAIORL are disabled in SH7124.
The initial value of PAIORL is H'0000.
Bit: 15
PA15
IOR
Initial value: 0
R/W: R/W
14
PA14
IOR
0
R/W
13
PA13
IOR
0
R/W
12
PA12
IOR
0
R/W
11
PA11
IOR
0
R/W
10
PA10
IOR
0
R/W
9
PA9
IOR
0
R/W
8
PA8
IOR
0
R/W
7
PA7
IOR
0
R/W
6
PA6
IOR
0
R/W
5
PA5
IOR
0
R/W
4
PA4
IOR
0
R/W
3
PA3
IOR
0
R/W
2
PA2
IOR
0
R/W
1
PA1
IOR
0
R/W
0
PA0
IOR
0
R/W
15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4)
PACRL1 to PACRL4 are 16-bit readable/writable registers that are used to select the functions of
the multiplexed pins on port A.
SH7125:
• Port A Control Register L4 (PACRL4)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
PA15 PA15 PA15
MD2 MD1 MD0
-
PA14 PA14 PA14
MD2 MD1 MD0
-
PA13 PA13 PA13
MD2 MD1 MD0
-
PA12 PA12 PA12
MD2 MD1 MD0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Jul. 25, 2008 Page 522 of 750
REJ09B0243-0400