SH7125_08 Datasheet, PDF (762/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Item
9.5.2 A/D Converter Activation
12.7.4 Sending a Break Signal
Table 13.3 Channel Select List
Page Revision (See Manual for Details)
319 Amended
A/D Converter Activation by A/D Converter Start
Request Delaying Function: The A/D converter can
be activated by generating A/D converter start request
signal TRG4AN or TRG4BN when the TCNT_4 count
matches the TADCORA or TADCORB value if the
UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D
converter start request control register (TADCR) is set
to 1. For details, refer to section 9.4.9, A/D Converter
Start Request Delaying Function.
472 Added
…Until TE bit is set to 1 (enabling transmission) after
initializing, TXD pin does not work. During the period,
mark status is performed by SPB0DT bit. Therefore, the
SPB0DT bit should be set to 1 at first (high level
output)….
483 Amended
Bit 2 Bit 1
CH2 CH1
0
0
Bit 0
CH0
0
A/D_0
AN0
Analog Input Channels
2-Channel Scan Mode* (Activated by software)
A/D_1
AN4
484
Figure 13.4 Example of
494
2-Channel Scanning
17.2.5 Block Division
580
Figure 17.4 Block Division of User 580
MAT
Added
Table of Activated by Triggers MTU2 or etc.
Amended
A/D conversion end (ADF)
CONADF bit in ADCSR = 0
CONADF bit in ADCSR = 1
Added
The user MAT can be erased in this divided-block units
and the erase-block number of EB0 to EB9 is specified
when erasing. The user MAT is divided into 16 Kbytes
(two blocks) for 32-Kbyte ROM version.
Amended
Rev. 4.00 Jul. 25, 2008 Page 742 of 750
REJ09B0243-0400