SH7125_08 Datasheet, PDF (26/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 1 Overview
1.2 Block Diagram
The block diagram of this LSI is shown in figure 1.1.
SH2
CPU
UBC
L bus (Iφ)
Internal bus
controller
ROM
RAM
I bus (Bφ)
Peripheral bus
controller
Peripheral bus (Pφ)
I/O
port
(PFC)
SCI CMT H-UDI INTC Power- WDT CPG MTU2 POE ADC
down
mode
control
[Legend]
ROM:
RAM:
UBC:
H-UDI:
INTC:
CPG:
WDT:
CPU:
On-chip ROM
On-chip RAM
User break controller
User debugging interface
Interrupt controller
Clock pulse generator
Watchdog timer
Central processing unit
PFC:
MTU2:
POE:
SCI:
CMT:
ADC:
Pin function controller
Multi-function timer pulse unit 2
Port output enable
Serial communication interface
Compare match timer
A/D converter
Figure 1.1 Block Diagram
Rev. 4.00 Jul. 25, 2008 Page 6 of 750
REJ09B0243-0400