SH7125_08 Datasheet, PDF (12/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

7.2.9 Break Data Mask Register B (BDMRB)............................................................... 124
7.2.10 Break Bus Cycle Register B (BBRB) ................................................................... 125
7.2.11 Break Control Register (BRCR) ........................................................................... 127
7.2.12 Execution Times Break Register (BETR)............................................................. 131
7.2.13 Branch Source Register (BRSR)........................................................................... 132
7.2.14 Branch Destination Register (BRDR)................................................................... 133
7.3 Operation ........................................................................................................................... 134
7.3.1 Flow of the User Break Operation ........................................................................ 134
7.3.2 Break on Instruction Fetch Cycle ......................................................................... 135
7.3.3 Break on Data Access Cycle................................................................................. 135
7.3.4 Sequential Break................................................................................................... 137
7.3.5 Value of Saved Program Counter ......................................................................... 137
7.3.6 PC Trace ............................................................................................................... 138
7.3.7 Usage Examples.................................................................................................... 139
7.4 Usage Notes ....................................................................................................................... 144
Section 8 Bus State Controller (BSC) ...............................................................147
8.1 Features.............................................................................................................................. 147
8.2 Address Map ...................................................................................................................... 147
8.3 Access to on-chip FLASH and on-chip RAM ................................................................... 147
8.4 Access to on-chip Peripheral I/O Register ......................................................................... 148
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)..................................... 151
9.1 Features.............................................................................................................................. 151
9.2 Input/Output Pins............................................................................................................... 157
9.3 Register Descriptions ......................................................................................................... 158
9.3.1 Timer Control Register (TCR).............................................................................. 162
9.3.2 Timer Mode Register (TMDR)............................................................................. 166
9.3.3 Timer I/O Control Register (TIOR)...................................................................... 169
9.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 188
9.3.5 Timer Interrupt Enable Register (TIER)............................................................... 189
9.3.6 Timer Status Register (TSR)................................................................................. 194
9.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 202
9.3.8 Timer Input Capture Control Register (TICCR)................................................... 203
9.3.9 Timer A/D Converter Start Request Control Register (TADCR) ......................... 205
9.3.10 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 208
9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 208
9.3.12 Timer Counter (TCNT)......................................................................................... 209
Rev. 4.00 Jul. 25, 2008 Page xii of xx