SH7125_08 Datasheet, PDF (480/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCSSR to 0
End
Figure 12.12 Sample Flowchart for Receiving Serial Data (2)
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into SCRSR in order from the LSB to the MSB. After receiving the
data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from
SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the
received data in SCRDR. If a receive error is detected, the SCI operates as shown in table
12.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will
not be set to 1 after reception; be sure to clear the RDRF flag to 0.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI).
Rev. 4.00 Jul. 25, 2008 Page 460 of 750
REJ09B0243-0400