SH7125_08 Datasheet, PDF (64/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.5.7 System Control Instructions
Table 2.16 System Control Instructions
Instruction
CLRT
CLRMAC
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
RTE
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
Operation
Code
0→T
0000000000001000
0 → MACH, MACL
0000000000101000
Rm → SR
0100mmmm00001110
Rm → GBR
0100mmmm00011110
Rm → VBR
0100mmmm00101110
(Rm) → SR, Rm + 4 → Rm 0100mmmm00000111
(Rm) → GBR, Rm + 4 →
Rm
0100mmmm00010111
(Rm) → VBR, Rm + 4 →
Rm
0100mmmm00100111
Rm → MACH
0100mmmm00001010
Rm → MACL
0100mmmm00011010
Rm → PR
0100mmmm00101010
(Rm) → MACH, Rm + 4 → 0100mmmm00000110
Rm
(Rm) → MACL, Rm + 4 → 0100mmmm00010110
Rm
(Rm) → PR, Rm + 4 → Rm 0100mmmm00100110
No operation
0000000000001001
Delayed branch,
Stack area → PC/SR
0000000000101011
1→T
0000000000011000
Sleep
0000000000011011
SR → Rn
0000nnnn00000010
GBR → Rn
0000nnnn00010010
VBR → Rn
0000nnnn00100010
Rn–4 → Rn, SR → (Rn) 0100nnnn00000011
Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011
Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011
Execution
Cycles
1
1
1
1
1
3
3
T Bit
0

LSB


LSB

3

1

1

1

1

1

1

1

5

1
1
4*

1

1

1

1

1

1

Rev. 4.00 Jul. 25, 2008 Page 44 of 750
REJ09B0243-0400