SH7125_08 Datasheet, PDF (431/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 12 Serial Communication Interface (SCI)
Section 12 Serial Communication Interface (SCI)
This LSI has three independent serial communication interface (SCI) channels. The SCI can
handle both asynchronous and clock synchronous serial communication. In asynchronous serial
communication mode, serial data communication can be carried out with standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial
communication between processors (multiprocessor communication function).
12.1 Features
• Choice of asynchronous or clock synchronous serial communication mode
• Asynchronous mode (channels 0 to 2 in the SH7125, channels 0 to 2 in the SH7124):
 Serial data communication is performed by start-stop in character units. The SCIF can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs
a standard asynchronous serial system. There are twelve selectable serial data
communication formats.
 Data length: 7 or 8 bits
 Stop bit length: 1 or 2 bits
 Parity: Even, odd, or none
 Multiprocessor communications
 Receive error detection: Parity, overrun, and framing errors
 Break detection: Break is detected by reading the RXD pin level directly when a framing
error occurs.
• Clock synchronous mode (channels 0 to 2 in the SH7125, channels 0 and 2 in the SH7124):
 Serial data communication is synchronized with a clock signal. The SCIF can communicate
with other chips having a clock synchronous communication function.
 Data length: 8 bits
 Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so high-
speed continuous data transfer is possible in both transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal
clock) or SCK pin (external clock)
• Choice of LSB-first or MSB-first data transfer (except for 7-bit data in asynchronous mode)
Rev. 4.00 Jul. 25, 2008 Page 411 of 750
REJ09B0243-0400