SH7125_08 Datasheet, PDF (685/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 19 Power-Down Modes
19.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the RAM operation in power-down
mode.
Bit: 7
6
5
4
3
2
1
0
MSTP
7
-
-
-
-
-
-
-
Initial value: 0
0
1
1
1
0
0
0
R/W: R/W R/W R/W R/W R/W R R R
Initial
Bit
Bit Name Value R/W
7
MSTP7
0
R/W
6

5 to 3 
2 to 0 
0
R/W
All 1
R/W
All 0
R
Description
Module Stop Bit 7
When this bit is set to 1, the supply of the clock to
the RAM is halted.
0: RAM operates
1: Clock supply to RAM halted
Reserved
This bit is always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Jul. 25, 2008 Page 665 of 750
REJ09B0243-0400