SH7125_08 Datasheet, PDF (251/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 9.42 Setting of Bits BTE1 and BTE0
Bit 1
Bit 0
BTE1
BTE0
Description
0
0
Enables transfer from the buffer registers to the temporary registers*¹
and does not link the transfer with interrupt skipping operation.
0
1
Disables transfer from the buffer registers to the temporary registers.
1
0
Links transfer from the buffer registers to the temporary registers with
interrupt skipping operation.*²
1
1
Setting prohibited
Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer
to section 9.4.8, Complementary PWM Mode.
2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the
timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and
4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with
interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to
0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer
transfer will not be performed.
Rev. 4.00 Jul. 25, 2008 Page 231 of 750
REJ09B0243-0400