SH7125_08 Datasheet, PDF (66/774 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 2 CPU
2.6 Processing States
The CPU has the five processing states: reset, exception handling, program execution, and power-
down. Figure 2.4 shows the CPU state transition.
From any state
when RES = 0
From any state
when RES = 1 and MRES = 0
Power-on reset state
RES = 0
Manual reset state
RES = 1
When internal power-on reset by WDT
or internal manual reset by WDT occurs.
Exception
handling state
RES = 1,
MRES = 1
Exception
processing
source
occurs
Exception
processing
ends
Reset state
NMI interrupt or IRQ
interrupt occurs
SSBY bit = 0
for SLEEP
instruction
Program
execution state
SSBY bit = 1 and
STBYMD bit = 1
for SLEEP
instruction
Sleep mode
Software
standby mode
Power-down mode
Figure 2.4 Transitions between Processing States
Rev. 4.00 Jul. 25, 2008 Page 46 of 750
REJ09B0243-0400